Embedded HPC & Reliable Accelerator Integration in the AI Age by Open EDA & Eco Systems
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Embedded HPC & Reliable Accelerator Integration in the AI Age by Open EDA & Eco Systems
Embedded HPC & Reliable Accelerator Integration in the AI Age by Open EDA & Eco Systems
Increasing emerging fields towards reliable embedded accelerator and processor integration, incl. High-Performance Computing(HPC) systems, are “essential and challenging forces” driving actual and future silicon technologies. This results in heterogenous multi-core (MC), various vector accelerator incl. artificial intelligence (AI) and networked cyber-physical systems (CPS) integration. Here, on one side increasing monolythic integration of cooperating computational and physical sensor components is necessary, e. g. in embedded and smart on-demand automatized environments as diverse as applied in communication/consumer, automotive/transportation, avionics, civil infrastructure, energy, healthcare, manufacturing (Industry 4.0), and also space appliances. Moreover, future complex dynamically adaptive and multi-domain electronic system integration tends to be more and more dependent on distributed real-time and embedded HPC availability. This results in the strong demand of newly operating decentralized/centralized intelligent, interconnected, and silicon technology integrated solutions, subject to increased performance needs to facilitate computationally intensive algorithms, power consumption to be minimized, as well as sufficient degrees of reliability and verifiability to employ digital systems in highly networked as well as safety-critical environments, e. g. in future embedded, incl.6G, automotive etc. system integration, driven by software-defined approaches. Existing technologies must evolve in order to meet such scalable and high requirements, whereas Open Source Hardware & Softwareincl. explainable AI-based components will also play key roles in this actual dynamic development. Multipurpose adaptivity, connectivity and reliability are crucial, especially in scaling down silicon technologies according to “Extending Moore” for future processor technologies incl. dynamically reconfigurable and AI-driven accelerators. This requires new open EDA approaches with standardized tool flows towards efficient heterogenous system integration. The talk will present important challenges of high-end heterogenous Multi-Core/Accelerator HPC platforms by reliable SoC and SiPhardware/software integration with smart, scalable, reliable & embedded accelerator & processor solutions. This includes corresponding Global Ecosystem discussions in the presence of RISC-V, national & European Chipact, 6G and automotive initiatives whereas necessary AI & chipdesign aspects have to be considered.
The talk will in addition sketch in this context some selected communication & automotive related project initiatives like Open6GHub (6G for Society and Sustainability - https://www.open6ghub.de/en/), EPI (European Processor Initiative - https://www.european-processor-initiative.eu), XANDAR (Safety and Security for Embedded Software Systems - https://xandar-project.eu), ZuSE-KI-mobil (Platform for energy-efficient AI processors in mobile applications - https://www.itiv.kit.edu/english/201_8016.php), and the national project CeCaS (CentralCarServer - https://www.itiv.kit.edu/english/201_8769.php), among others.
Date and Time
- Date: 14 Apr 2025
- Time: 01:30 PM -03 to 03:00 PM -03
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Location
- Av. Bento Gonçalves, 9500 - UFRGS Campus do Vale
- Auditório do Instituto de Informática
- Porto Alegre, Rio Grande do Sul
- Brazil 91509-900
- Building: 43413
Hosts
- South Brazil Sect,CAS04 Rio Grande Do Sul
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- Co-sponsored by UFRGS
Speakers
Jurgen Becker of Karlsruhe Institute of Technology (KIT)
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