Escuela de verano de diseño de circuitos integrados. Se enseña microelectrónica, con énfasis en la aplicación práctica en proyectos de diseño de circuitos fabricables. Se realizan dos tracks paralelos, en flujo analógico y digital. Co-sponsored by: Timeless-IC Bldg: B, Av. España 1680, Valparaiso, Valparaiso, Chile
XVIII IEEE Summer School on Computational Intelligence (EVIC) December 13-15, 2023 Facultad de Ciencias Físicas y Matemáticas, Universidad de Chile Beauchef 851, Santiago (Metro Toesca or Parque O’higgins), Chile https://www.evic.cl/ Poster Competition 1st call for extended abstracts deadline: November 5th, 2023 (https://www.evic.cl/?page_id=235) ================================================================ The XVIII Summer School on Computational Intelligence will take place at the Faculty of Mathematical and Physical Science of the University of Chile, Santiago. It is jointly organized by the Chilean Chapter of the IEEE Computational Intelligence Society and the Initiative for Data and Artificial Intelligence of the University of Chile. The summer schools aims to promote Computational Intelligence, bringing together areas such as Intelligent Control Systems, Astroinformatics, Biomedical Engineering, Bio-Informatics, Robotics, Computer Vision, Computational Neuroscience, Science Data, and Big Data, among others, in order to disseminate the basic knowledge and the latest research advances to students, professors and professionals from Chile and other Latin American countries. During the Summer School, a Student Poster Competition on Computational Intelligence will be held. ==== Confirmed speakers ==== - Danilo Mandic - Imperial College London (United Kingdom) - Andrés Muñoz Medina - Google Research - Gabriel León - Science Communicator - Pamela Guevara - AC3E and University of Concepción - Igor Škrjanc - University of Ljubljana - Enzo Ferrante - CONICET & National University of Litoral ==== Tutorials ==== - Gloria Henríquez - Center for Mathematical Modelling - Rodolfo Núñez - Entel & TripleTen - Jorge Silva - University of Chile - Benjamín Herrmann - Universidad de Chile - Javiera Castillo - École Polytechnique Féderale de Laussane - Iván Castro - Amazon Web Services - Christopher P. Ley- Center for Mathematical Modelling - Gonzalo Ríos - NoiseGrasp ==== Local organizing committee (University of Chile) ==== Felipe Tobar Dominique Hermosilla Camilo Carvajal Reyes ==== Important dates ==== - Abstract submission deadline: November 5th, 2023 - Abstracts acceptance result: November 27th, 2023 ===== Paper submission ===== Authors should submit their articles in English as PDF files following the IEEE style guidelines for conference proceedings (limited up to 2 pages (US letter size) of content and 1 page for images). The submission must include the following sections: Introduction, methods, results, discussion and conclusions. Affiliation should include the name of the student participating in the competition and the name of the co-authors. (https://www.evic.cl/?page_id=235) Submit your work in PDF format at the following link (https://openreview.net/group?id=EVIC.cl/2023/Summer_School) Posters will be selected based on the quality of the extended abstract. The decision notification will be sent by electronic mail. Posters should be posted according to the schedule which will be noted in the program. A committee of three experts will evaluate the posters and assign the first, second and third places. The awards will be announced on December 14th, 2023. Facultad de Ciencias Físicas y Matemáticas, Universidad de Chile , Beauchef 851, Santiago, Santiago, Region Metropolitana, Chile
Evento de difusión técnica dirigido a profesionales y estudiantes vinculados con el sector eléctrico ecuatoriano tendiente a motivar el aprovechamiento de energías renovables en mini y micro centrales de generación distribuida. Co-sponsored by: DEPARTAMENTO DE ENERGÍA ELÉCTRICA - ESCUELA POLITÉCNICA NACIONAL Speaker(s): , Gabriel Salazar Auditorio 1, 5to piso del Edificio de Aulas y Relación con el Medio Externo (EARME) , Av. Toledo y Madrid., Quito, Pichincha, Ecuador
El seminario está enfocado a brindar conocimientos y experiencias para el aprovechamiento de la infraestructura de cuartos limpios ubicada en el Centro de Nanociencias y Micro y Nanotecnologías del Instituto Politécnico Nacional en el desarrollo de dispositivos semiconductores y circuitos integrados a nivel nacional. Co-sponsored by: Section of Solid-State Electronics (SEES), CINVESTAV-IPN and Center for Nanociences and Micro and Nanotechnologies of the National Polytechnic Institute. Speaker(s): Dr. Norberto Hernández, Dr. Arturo Torres, Dr. Isaí Hernández Agenda: Horarios Jueves 14 de diciembre-CNMN-IPN 11:00 a 11:10 Bienvenida Dr. Oscar Camacho Nieto, Director del CNMN. 11:10 a 11:50 1ª. Conferencia: Laboratorio Nacional de Micro y Nanotecnología (LNunT) Dr. Norberto Hernández Como, Especialista del CNMN y IEEE Senior member. 11:50 a 12:30 2ª. Conferencia: Fabricación de dispositivos CMOS Dr. Arturo Torres Sanchez, Posdoctorante en el LNunT. 12:30 a 13:10 3ª. Conferencia: Evaluación de la estructura MIS hacia los transistores de película delgada. Dr. Isai Salvador Hernandez Luna, IEEE member, Posdoctorante en el LNunT. 13:10 a 13:30 Avisos para próximos eventos. Dr. Cuauhtémoc León Puertos, Subdirector de Micro y Nanotecnología del CNMN. Room: Sala de reuniones, Bldg: Centro de Nanociencias y Micro y Nanotecnologías, Av. Luis Enrique Erro S/N, Unidad Profesional Adolfo López Mateos, Zacatenco, Ciudad de México, Mexico, Mexico, 07738
Welcome to Global Webinar co-sponsored by Pikes Peak Section and Panama Computer Society Chapter and co-hosted by a number of Chapters worldwide. The Chip Act: A New Era in US Semiconductors David Bondurant, Vertical Memory Matt Francis, Ozark IC This presentation will review 50-years of Semiconductor and Computer developments and historical competition between countries that developed. We observe the historical scaling of semiconductors (Moore’s Law) and the fact the Moore’s Law scaling is reaching it’s end. We review Beyond Moore changes to semiconductor processing and packaging technology required to continue computer performance improvement and why control of leading edge semiconductor and packaging manufacturing is now strategic. The Chip Act is the United States response to demands of Beyond Moore requirements and need to bring manufacturing closer to home. We review the Chip Act and update on it’s developments during 2023. Speaker(s): David, Matt, Agenda: Welcome Presentation Discussion and Questions Virtual: https://events.vtools.ieee.org/m/388526
