Projects administered by the TTSC: 
| Project | Title | IEEE SA Lifecycle State |
| 1149.1 | Standard for Test Access Port and Boundary-Scan Architecture | 3 – Drafting a standard |
| 1149.4 | Standard for a Mixed-Signal Test Bus6 – Maintaining a standard | 6 – Maintaining a standard |
| 1149.6 | Standard for Boundary-Scan Testing of Advanced Digital Networks | 6 – Maintaining a standard |
| 1149.7 | Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture | 6 – Maintaining a standard |
| 1149.10 | Standard for High-Speed Test Access Port and On-Chip Distribution Architecture | 6 – Maintaining a standard |
| 1450 | Standard Test Interface Language (STIL) for Digital Test Vector Data | 6 – Maintaining a standard |
| 1450.1 | Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Semiconductor Design Environments | 5 – Gaining Final Approval |
| 1450.4 | Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Test Flow Specification | 6 – Maintaining a standard |
| 1450.6.2 | Standard for Memory Modeling in Core Test Language | 3 – Drafting a standard |
| 1500 | Standard Testability Method for Embedded Core-based Integrated Circuits | 6 – Maintaining a standard |
| 1581 | Standard for Static Component Interconnection Test Protocol and Architecture | 3 – Drafting a standard |
| 1687 | Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device | 3 – Drafting a standard |
| 1687.1 | Standard for the Application of Interfaces and Controllers to Access 1687 IJTAG Networks Embedded Within Semiconductor Devices | 3 – Drafting a standard |
| 1687.2 | Standard for Describing Analog Test Access and Control | 3 – Drafting a standard |
| 1804 | Standard for Fault Accounting and Coverage Reporting(FACR) for Digital Modules | 6 – Maintaining a standard |
| 1838 | Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits | 3 – Drafting a standard |
| 2427 | Standard for Analog Defect Modeling and Coverage | 4 – Balloting a standard |
| 2654 | Standard for System Test Access Management (STAM) to Enable Use of Sub-System Test Capabilities at Higher Architectural Levels | 3 – Drafting a standard |
| 2929 | Standard for System-level State Extraction for Functional Validation and Debug | 3 – Drafting a standard |
| 3405 | Standard for Chiplet Interconnect Test and Repair | 3 – Drafting a standard |
Inactivated projects:
| Project | Title | IEEE SA Lifecycle State |
| 1149.8.1 | Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and/or Active Components | Inactive |
| 1450.2 | Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for DC Level Specification | Inactive |
| 1450.3 | Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std. 1450-1999) for Tester Target Specification | Inactive |
| 1450.6 | Standard Test Interface Language (STIL) for Digital Test Vector Data-Core Test Language (CTL) | Inactive |
| 1450.6.1 | Standard for Describing On-Chip Scan Compression | Inactive |