Pavan Hanumolu's Course on Microelectronics (AGH University, Kraków)
#clock
#SerDes
#circuits
#microelectronics
#electronics
#integrated
#design
#pll
#asic
#ic
Course on selected aspects of microelectronics design:
- DFE (Decision Feedback Equalizer)
- Clock and data recovery
- Charge-pump phase-locked loops (CPLLs)
- Digital PLLs
- Analog/digital (hybrid) PLLs
- Multiplying delay-locked loops
- RC oscillators
Date and Time
Location
Hosts
Registration
- Start time: 26 May 2025 11:00 AM UTC
- End time: 28 May 2025 04:00 PM UTC
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- AGH University of Kraków
- Krakow, Malopolskie
- Poland 30-059
- Building: B1
- Room Number: H24 lecture hall
- Contact Event Host
- Co-sponsored by Silicon Creations
- Starts 03 March 2025 11:00 PM UTC
- Ends 25 May 2025 10:00 PM UTC
- No Admission Charge
Agenda
Day 1: 13:00 - 18:00 CEST
- Equalization (1h)
- DFE (1h)
- Clock and data recovery (2h)
Day 2: 13:00 - 18:00 CEST
- Charge-pump PLLs (1h)
- Digital PLLs (1h)
- Analog-Digital (Hybrid) PLLs (1h)
- Multiplying Delay-Locked Loops (1h)
Day 3: 13:00 - 16:00 CEST
- RC Oscillators (2h)
Coffee breaks included.