Title: Trend and Opportunities for High-Speed (GS/s) ADCs

#circuits #cmos #power #electronics #signal #computer #low-power #analog
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IEEE

Santa Clara Valley Section CH06184

Solid-State Circuits Society Chapter SSC37

Title: Trend and Opportunities for High-Speed (GS/s) ADCs
 
Abstract: Analog to digital converter (ADC) is a critical building block for most electronic systems. Many
wideband electronic systems (such as wireless and wireline communications) favor digitization of analog
signal with increasing bandwidth (>GHz) and fidelity; at the same time, demand a low area/power
consumption. It leads to a great interest in high-speed ADCs in recent years. In this talk, I will describe
the recent trend of high-speed (>GS/s) ADC. Many existing works leverage massively interleaved SAR
ADCs. On the other hand, there are emerging opportunities to quantize the analog signal in time domain
with high speed. I will introduce a few ADC architectures and/or techniques that demonstrate promises
in achieving high conversion rate but at a low area and/or power consumption, including some silicon
examples developed in my research group.

  Date and Time

  Location

  Hosts

  Registration


  • Date: 21 Feb 2025
  • Time: 04:00 PM to 06:00 PM
  • All times are (UTC-08:00) Pacific Time (US & Canada)
  • Add_To_Calendar_icon Add Event to Calendar
  • 500 El Camino Real
  • Santa Clara University
  • Santa Clara, California
  • United States 95053
  • Building: Bergin Hall
  • Room Number: 116
  • Contact Event Host
  • Starts 06 February 2025 10:00 PM
  • Ends 21 February 2025 06:00 PM
  • All times are (UTC-08:00) Pacific Time (US & Canada)
  • No Admission Charge

  Speakers

Mike Chen

Topic:

Title: Trend and Opportunies for High-Speed (GS/s) ADCs

Title: Trend and Opportunities for High-Speed (GS/s) ADCs
 
Abstract: Analog to digital converter (ADC) is a critical building block for most electronic systems. Many
wideband electronic systems (such as wireless and wireline communicaons) favor digitization of analog
signal with increasing bandwidth (>GHz) and fidelity; at the same time, demand a low area/power
consumption. It leads to a great interest in high-speed ADCs in recent years. In this talk, I will describe
the recent trend of high-speed (>GS/s) ADC. Many existing works leverage massively interleaved SAR
ADCs. On the other hand, there are emerging opportunies to quantize the analog signal in time domain
with high speed. I will introduce a few ADC architectures and/or techniques that demonstrate promises
in achieving high conversion rate but at a low area and/or power consumption, including some silicon
examples developed in my research group.
 

Biography:

Mike Shuo-Wei Chen is currently a Professor at Electrical and Computer Engineering Department, University of Southern California..

He received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998 and the M.S. and Ph.D. degree from University of California, Berkeley, in 2002 and 2006, all in electrical engineering.

As a graduate student researcher, he proposed and demonstrated the first asynchronous SAR ADC architecture, which has been adopted today for low-power high-speed analog-to-digital conversion products in industry. Since 2006, he has been a member of Analog IC Group at Atheros Communications (now Qualcomm-Atheros), Santa Clara, CA, working on mixed-signal and RF circuits for various wireless communication products. After joining USC in 2011, he leads an analog mixed-signal circuit group, focusing on high-speed low-power data converters, AI/ML computing, RF frequency synthesizers, wireless/wireline transceiver designs, analog design automation, non-uniformly sampled circuits and systems. His students and himself have a lot of fun exploring new circuit architectures that excel beyond the technology limitation.

Dr. Chen was the recipient of Qualcomm Faculty Award in 2019, NSF Faculty Early Career Development (CAREER) Award and DARPA Young Faculty Award (YFA) both in 2014. He also achieved an honourable mention in the Asian Pacific Mathematics Olympiad, 1994, UC Regents’ Fellowship at Berkeley in 2000 and Analog Devices Outstanding Student Award for recognition in IC design in 2006.

In terms of society services, Dr. Chen has been serving as an associate editor of IEEE Solid-State Circuits Letters (SSC-L), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), as well as a TPC member of conferences in IEEE Solid-State Circuits Society, such as IEEE International Solid State Circuits Conference (ISSCC), IEEE VLSI Circuits Symposium (VLSIC), and IEEE Custom Integrated Circuits Conference (CICC). He has served as Distinguished Lecturer for IEEE Solid-State Circuits Society (SSCS). He is an IEEE Fellow, elevated via SSCS.

Biography:

Biography:

Mike Shuo-Wei Chen is currently a Professor at Electrical and Computer Engineering Department, University of Southern California..

He received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998 and the M.S. and Ph.D. degree from University of California, Berkeley, in 2002 and 2006, all in electrical engineering.

As a graduate student researcher, he proposed and demonstrated the first asynchronous SAR ADC architecture, which has been adopted today for low-power high-speed analog-to-digital conversion products in industry. Since 2006, he has been a member of Analog IC Group at Atheros Communications (now Qualcomm-Atheros), Santa Clara, CA, working on mixed-signal and RF circuits for various wireless communication products. After joining USC in 2011, he leads an analog mixed-signal circuit group, focusing on high-speed low-power data converters, AI/ML computing, RF frequency synthesizers, wireless/wireline transceiver designs, analog design automation, non-uniformly sampled circuits and systems. His students and himself have a lot of fun exploring new circuit architectures that excel beyond the technology limitation.

Dr. Chen was the recipient of Qualcomm Faculty Award in 2019, NSF Faculty Early Career Development (CAREER) Award and DARPA Young Faculty Award (YFA) both in 2014. He also achieved an honourable mention in the Asian Pacific Mathematics Olympiad, 1994, UC Regents’ Fellowship at Berkeley in 2000 and Analog Devices Outstanding Student Award for recognition in IC design in 2006.

In terms of society services, Dr. Chen has been serving as an associate editor of IEEE Solid-State Circuits Letters (SSC-L), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), as well as a TPC member of conferences in IEEE Solid-State Circuits Society, such as IEEE International Solid State Circuits Conference (ISSCC), IEEE VLSI Circuits Symposium (VLSIC), and IEEE Custom Integrated Circuits Conference (CICC). He has served as Distinguished Lecturer for IEEE Solid-State Circuits Society (SSCS). He is an IEEE Fellow, elevated via SSCS.

Address:Department of Electrical and Computer Engineering, 3737 Watt Way, University of Southern California , Los Angeles, California, United States, 90089




Agenda

Networking: 4:00 pm - 5:00 pm (PT)

Presentation: 5:00 pm - 6:00 pm (PT)


IEEE SCV section SSCS chapter