THE VLSI IMPLEMENTATION OF HIGH THROUGHPUT LOW POWER DESIGN OF PIPELINE CELLULAR ARRAY

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The VLSI Implementation of High Throughput Low Power Design Of Pipeline Cellular Array.

There has been increasing interest in the design of array processors for the last several years. The array processors require adders and subtractors as the hardware instead of software routines. There have been several research papers in the literature on the design of arithmetic circuits using arrays. There is increased interest in the VLSI implementation of such circuits.

With the coming of advanced-level FPGAs, there is an interest in the implementation of such circuits on FPGAs. With the increasing requirement for hot chips and their use in all walks of life, the design and implementation of array processors has become more and more truthful research problems.
The problem of array computing has been tackled by the design and implementation of a generalized pipeline array. Algorithms are developed which will result in the design of low power high, throughput generalized pipeline array. This array can do arithmetic operations like addition, subtraction, multiplication, squaring, and square rooting with the help of hardware. The strategy used is to simply extending Verilog code from one level to the next level of the design and keeping basic cells such as arithmetic cell and control cell same. The pipeline array processors for 5,7,9 rows are implemented. The algorithms can be extended to any number of rows. The implementation of the processors is done using Verilog language and Cadence tools. The algorithms for VLSI design implementation for pipeline arrays have been taken up in this work. The GDS of the designs can be sent to any silicon foundry and get the fabricated chip back. The procedure developed should be applicable to different technologies, such as 500nm and below. It is hoped that these algorithms can go a long way as one step further in the area of computing and special applications. 

Discussion on the topic :

THE VLSI IMPLEMENTATION OF HIGH THROUGHPUT LOW POWER DESIGN OF PIPELINE CELLULAR ARRAY

 The VLSI Implementation of High Throughput Low Power Design Of Pipeline Cellular Array.

Lectures:

Otman Ali Awin PhD student at Wayne State University, Detroit Michigan
Topic: The VLSI Implementation of High Throughput Low Power Design Of Pipeline Cellular Array.