A set of guidelines is presented in this recommended practice for the development of energy-efficient and power-proportional digital architectures so that energy is only consumed when computations are under way and energy is reduced in the non-operating state. The purpose of this practice is to provide guidelines for the designers and developers of digital architectures for creating power-proportionality at different levels of the system.

This recommended practice specifies a set of guidelines for the development of power-proportional digital architectures so that energy is only consumed when computations are underway. Digital architectures could encompass individual devices such as CPUs and systems on chip (SoCs), or specialized computing platforms such as smartphones, smartwatches, and individual servers, or larger systems and networks of distributed compute and data servers. These architectures could consist of components such as processors, specialized accelerators, memory, interconnects, storage, networks, and power supplies. In power-proportional power supplies, various techniques can be used to conserve and store energy when computation is halted, keeping it available for immediate use upon restart. The objective of such power supplies is to respond to nanosecond variations in the computing load in the presence of complementary metal-oxide semiconductor (CMOS) static power dissipation.

The purpose of this recommended practice is to provide a set of guidelines for the designers and developers of digital architectures that help ensure that power is consumed mostly when useful computational work is under way, and is consumed the least when idle.