A method is provided for specifying power intent for an electronic design, for use inverification of the structure and behavior of the design in the context of a given power managementarchitecture, and for driving implementation of that power management architecture. The methodsupports incremental refinement of power intent specifications required for IP-based design flows.

This standard establishes a format used to define the low-power design intent for electronic systems and electronic intellectual property (IP). The format provides the ability to specify the supply network, switches, isolation, retention, and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low-power design specification and the logic design specification captured via other formats [e.g., standard hardware description languages (HDLs)].

The purpose of this standard is to provide portable low-power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification, and implementation flow.