Aspects of fault models as they are relevant to the generation of test patterns for digital circuits are formalized in this standard. Fault counting, fault classification, and fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model are included in the scope. It shall be incumbent for fault coverage to be reported in a uniform way on all ATPG tools (that comply with this standard). The generation of a uniform coverage (and, hence, a uniform test quality) metric for large chips [including systems-on-chips (SOCs)] with different cores and modules for which test patterns have been independentl...

This standard formalizes aspects of the stuck-at fault model as they are relevant to the generation of test patterns for digital circuits. Its scope includes a) fault counting, b) fault classification, and c) fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model. Fault grading and simulation is limited to the Verilog gate level representation of a digital circuit. With this standard, it shall be incumbent on all ATPG tools (that comply with this standard) to report fault coverage in a uniform way. This can facilitate the generation of a uniform coverage (and hence a test quality) metric ...

Digital circuits have various structural representations either in high level hardware description languages (HDLs) which can then be synthesized, or in netlist forms. Commercial tools today for Automatic Test Pattern Generation (ATPG) using algorithmic techniques operate on a structural netlist of the Design Under Test (DUT). The test quality signoff process mandatorily includes a minimal coverage requirement, to19 be obtained using these ATPG tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across differe...