This International Standard provides a set of tools with which to implement a Futurebus+¨ architecture. This high-performance bus-based system architecture provides a wide range of performance and cost scalability over time for multiple generations of single- and muliple-bus multiprocessor systems. This document, a companion standard to ISO/IEC 10857:1994 [ANSI/IEEE Std 896.1,1994 Edition], builds on the logical layer by adding requirements for three military profiles. It is to these profiles that products will claim conformance. Othere specifications that may be required in conjunction with this International Standard are [ISO/IEC Std 10857: 1994 [ANSI/IEEE Std 896.1, 1994 Edition], IEEE Std 896.2-1991, IEEE Std 896.2a-1994, IEEE Std 896.3-1993, IEEE Std 896.4-1993, IEEE P896.4a, IEEE Std 896.9-1994, IEEE Std 1101.3-1993, IEEE Std 1101.4-1993, IEEE Std 1212-1991, IEEE Std 1194.1-1991, IEEE Std P1394, IEEE Std 1301-1991, and IEEE Std 1301.1-1991.

The initial work in development of the Futurebus+™specification was done under the auspices of the IEEE Computer Society Microprocessor Standards Committee. In 1988, both the United States Navy's Next Generation Computer Resources (NGCR) Backplane Standards Committee and the VFEA International Trade Association (VITA), a trade association of both VME64 manufacturers and users, agreed to join the IEEE in revising ISO/IEC 10857 :1994 [ANSI/IEEE Std 896.1, 1994 Edition].1 In early 1989, the Multibus Manufacturers Group (MMG), a trade association of both Multibus I and Multibus II manufacturers and users, also agreed to join this effort. The primary goal of all four groups (IEEE, U.S. Navy, VITA, and MMG) was to provide a new microprocessor bus standard that would be commercially viable and that would be acceptable to the two manufacturer groups and the three user communities.