The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus at its highest performance--32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered.

This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard.The bus standard must have a design-in lifetime of 10 years with backward compatibility.The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time.The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1, 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements.Options within the standard will be clearly identified.The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system.The standard is intended to support heterogeneous processor types in ...